1. Field of the Invention
The present invention relates to a semiconductor device such as an field effect transistor, particularly a vertical field effect transistor (MOSFET) and a method for manufacturing the semiconductor device.
2. Description of the Related Art
A MOS transistor such as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an IGBT (Insulated Gate Bipolar Transistor) can be exemplified as a semiconductor device for electric power control. In view of energy saving, recently, it is required the efficiency of the semiconductor device is enhanced. With the semiconductor device for electric power control, the electric conduction loss, that is, the on-resistance of the device is reduced in order to enhance the efficiency of the semiconductor device. As of now, the reduction of on-resistance would be conducted by miniaturizing the cells of the semiconductor device.
Alternatively, a trench gate structure is applied to the semiconductor device so that the size of each cell can be remarkably miniaturized while the channel widths in the semiconductor device can be maintained. At present, the cells of the semiconductor device are much more miniaturized by using the trench gate structure so that the on-resistance of the semiconductor device can be remarkably improved. Moreover, second trenches are formed at the respective source regions so as to form the source contacts with the side walls of the second trenches. Such a structure is called as a “trench contact structure”.
Referring to Reference 1, for example, a plurality of contact trenches are arranged in the direction along the gate trenches so as to increase the contact areas between the respective source electrodes and source regions and thus, to reduce the on-resistance of the semiconductor device. Each contact trench is configured such that a through hole is formed at the area to be formed as a source region between the adjacent gate trenches and the side wall of the through hole is entirely rendered the source region.
In Reference 1, however, since each cell is miniaturized, the embedding condition of electrode material for forming the source electrode into the contact trench per cell is deteriorated so that some voids may be formed in the resultant source electrode. As a result, the contact resistances in the respective contact trenches may be increased so that the on-resistance of the semiconductor device may be also increased. In Reference 2, in this point of view, each contact trench is shaped linearly so as to improve the embedding condition of the electrode material therein and thus, improve the on-resistance of the semiconductor device through the reduction in contact resistance of each contact trench.
[Reference 1] JP-A 2006-59940 (KOKAI)
[Reference 2] JP-A 2006-294853 (KOKAI)
In Reference 2, however, impurity regions are formed so as to embed the corresponding contact trenches so that the contacts between the source electrodes and the impurity regions are formed at the upper sides of the corresponding contact trenches. As a result, the Vsus (Vsustain) tolerance of the semiconductor device such as a transistor as described above may be weakened.
In References 1 and 2, however, since each contact trench is formed by means of anisotropic etching such as RIE (reactive ion etching), impurities are implanted into the side wall of each contact trench when the impurity region is formed so that the contact resistance per cell, that is, the on-resistance of the semiconductor device is increased.